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1. Why SiC & GaN gate layout is different

Compared to silicon MOSFETs:

• SiC / GaN switch much faster (50–200 V/ns and above)
• Gate charge is lower, but gate is more sensitive to dV/dt
• Parasitic inductances and capacitances dominate behavior

Result: A “good enough” MOSFET layout is often not acceptable for SiC/GaN.

2. Minimize the gate loop inductance

The gate loop consists of:

• Gate driver output pins
• Gate resistor
• Gate pin of SiC/GaN device
• Source / emitter return path back to the driver

Layout rules:

• Place driver as close to the gate pins as possible
• Use short, wide traces or copper shapes for gate and return
• Route gate and return as a tight pair over solid ground plane
• Avoid vias in the gate loop; if unavoidable, use multiple vias in parallel

3. Kelvin source connection

Most high-performance SiC MOSFETs and GaN FETs provide a dedicated Kelvin source (S_kelvin) pin.

Use it for the gate driver return:

• Connect driver ground to the Kelvin source, not to power source lead
• Route Kelvin source line short and separate from power source trace
• Do not share this trace with high current paths

4. Gate resistor placement and split resistors

Gate resistor is the main tool to control turn-on / turn-off speed and ringing.

• Place the resistor directly at the gate pin of the device
• Use separate resistors for turn-on and turn-off if needed (R_on, R_off)
• Route gate trace driver → resistor → gate pin, no stubs

Split gate resistors help tune dV/dt and reduce EMI without sacrificing efficiency completely.

5. Controlling dV/dt and Miller effect

High dV/dt can couple through Miller capacitance (C_gd) and cause unwanted turn-on of the opposite device in a half-bridge.

• Use proper gate resistor value and potentially negative gate bias (e.g. −2…−5 V)
• Minimize common source inductance with Kelvin source
• Keep drain-node (switch node) copper compact and away from gate traces
• For GaN, follow vendor-specific layout rules for common-source / cascode structures

6. Isolated gate drivers and creepage/clearance

Many SiC/GaN applications operate from high DC bus voltages (400–800 V and above), so isolated drivers are required.

• Respect creepage and clearance rules for isolation barriers
• Keep primary and secondary grounds separated and well defined
• Do not run noisy gate loops across the isolation boundary
• Use local supply decoupling on driver secondary side (close to V_DD, V_SS)

7. Decoupling the gate driver supply

Gate driver supply (e.g. +15 V / −3 V) must be rock-solid:

• Place ceramic capacitors (e.g. 100 nF + 1 µF) very close to driver pins
• Use short, wide traces for supply and return
• Consider additional bulk capacitor (4.7–47 µF) near driver cluster

8. Half-bridge layout: symmetry and loop control

In half-bridge SiC/GaN stages, the layout must be symmetric:

• Keep high-side and low-side gate loops similar in length and geometry
• Minimize power loop inductance (DC+ → FET → inductor/transformer → DC−)
• Use compact, planar loops instead of long U-shaped routes
• Place DC-link capacitors as close as possible to the half-bridge

9. EMI and measurement considerations

With SiC/GaN edges, measurement technique is critical:

• Use differential probes for gate and switch-node measurements
• Use probe ground springs, not long ground leads
• Expect significant common-mode noise on probes and scopes

10. Quick layout checklist for SiC & GaN gate drivers

• Driver placed as close as possible to power devices
• Gate loop short, tight and over solid reference plane
• Kelvin source used for gate return (if available)
• Gate resistor(s) at the gate pin
• Switch node copper minimized and kept away from gate traces
• Driver supply decoupled with ceramics near pins
• Isolation creepage/clearance respected
• Symmetric half-bridge geometry and tight DC-link loop

11. Conclusion

SiC and GaN devices can deliver outstanding efficiency and power density, but only with a disciplined gate driver layout. Treat gate and source connections as a high-frequency transmission path, not just “a few copper traces”, and follow these rules early in the design — before the first board spin.