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1. Identify the noisy current loops

Before you even route traces, identify the critical high di/dt loops:

• Input switch loop (VIN → high-side switch → SW node → return)
• Freewheel/rectifier loop (SW node → diode/MOSFET → output cap → return)
• Gate drive loop (driver → MOSFET gate → source/return)

Rule: each noisy loop must be as small and tight as possible, placed over a solid ground plane.

2. Switch node routing (“SW”)

The switch node is the noisiest point of any DC/DC converter. Mistakes here guarantee EMI trouble.

• Keep SW copper area as small as functionally possible
• Avoid long traces from SW to inductor/diode
• Do not route signals under or near SW polygon
• Do not run SW close to board edges or cables
• If you need copper for heat, use controlled “shielded” shapes and planes below

For multi-phase converters, keep each phase’s SW node compact and symmetric.

3. Ground strategy for DC/DC converters

A robust EMC layout requires a deliberate ground strategy:

• Use a solid, unbroken GND plane under the DC/DC area
• Connect high-frequency power grounds and quiet control ground at a single star point
• Avoid long “ground traces” – use planes and stitching vias instead
• Place input and output capacitors so that their ground pads are very close to switch and rectifier nodes

4. Input filtering and connector side

Conducted EMI is strongly influenced by the input filter layout and how the converter connects to the outside world:

• Place the input EMI filter (CM/DM chokes, capacitors) right at the connector
• Keep noisy converter loops physically separated from connector area
• Route filtered and unfiltered grounds with clear separation and a defined join point
• Avoid routing SW or gate drive traces towards the connector side

5. Output filtering and sense lines

On the output side, ripple and switching spikes can couple back into cables and loads:

• Place output capacitors close to rectifier/MOSFET and load return
• Use small, low-ESL ceramic caps directly near the converter and bulk caps slightly further
• Route sensing lines (FB, remote sense) away from SW node and noisy loops
• If remote sensing is used, twist or route sense traces as a pair over solid ground

6. Gate drive layout

Poor gate drive routing causes ringing, overshoot and unnecessary EMI:

• Keep gate traces as short as possible
• Route gate and gate-return (driver ground/source) as a tight pair
• Avoid running gate traces parallel to sensitive analog or digital lines
• Place gate resistor close to the MOSFET gate pin

7. Snubbers, RC dampers and shielding copper

Snubbers and damping networks are powerful tools — but only if placed correctly:

• Place RC snubbers directly between SW and ground on the same local island
• Keep their loop area tiny (short tracks, no long detours)
• Use dedicated “shield” copper shapes connected to ground near noisy traces
• Do not create big floating copper islands; always connect them to a low-impedance reference

8. Component placement order (before routing)

A good EMI layout is 80 % placement and only 20 % routing. Place parts in this order:

1. DC/DC IC, power switch(es), rectifier(s)
2. Input and output capacitors (tight loops)
3. Inductor/transformer (coupled to SW node)
4. EMI filter components and connector
5. Sense/feedback network, compensation components
6. Control IC decoupling, reference bypass

Only after this start routing, always checking whether the main loops remain small and well referenced to ground.

9. PCB stackup choice for low EMI

For serious EMI/EMC performance, a 4-layer PCB with solid internal ground is strongly recommended:

• Top: DC/DC components, critical loops
• L2: Solid GND plane
• L3: Power rails + slow control
• Bottom: Secondary routing and low-speed I/O

This minimizes return path inductance and makes common-mode noise easier to control.

10. Probing technique for EMI debugging

Many “mystery” EMC failures are simply measurement issues. For consistent results:

• Use a short ground spring on the oscilloscope probe, not a long wire
• Measure directly across the component pins, not at remote test points
• Use differential probes where possible
• Use near-field probes to locate hot spots around SW node and inductors

11. Final EMI/EMC layout checklist

Before releasing Gerbers, verify:

• All high di/dt loops placed and routed as tight as possible
• SW node area minimized and kept away from connectors and signals
• Solid ground plane under the converter, no unnecessary splits
• Input/output filters located close to connector and converter
• Gate drive traces short, with clear return paths
• Snubbers and damping networks placed with tiny loop area
• Sense/feedback lines routed away from noise sources
• Stackup suitable for EMI goals (4-layer minimum for demanding designs)

12. Conclusion

A good EMI/EMC layout for DC/DC converters is a list of small, boring decisions that add up to big test margins. Use this checklist as part of your design review, and your chances of passing EMC on the first or second iteration increase dramatically.